Mentor Graphics CEO to Keynote 2005 Design & Verification Conference & Exhibition
WILSONVILLE, Ore.—(BUSINESS WIRE)—Feb. 11, 2005—
Mentor Graphics Corporation (NASDAQ:MENT) today
announced that Walden C. Rhines, the company's chairman and CEO, will
keynote the 2005 Design & Verification Conference & Exhibition (DVCon)
on February 15 at the Double Tree Hotel in San Jose, California. Dr.
Rhines will explore how verification over the past twenty years has
been driven by successive waves of innovations, moving designers up
the layers of abstraction. New techniques are emerging that will
support more effective verification at the multiple levels required
for advanced SoC design: at the block, intra-block and system level.
What: Mentor Graphics keynote by Walden C. Rhines,
Chairman and CEO, Mentor Graphics Corporation,
at DVCon 2005.
When: Tuesday, February 15 at 8:30 a.m.
Where: Donner Ballroom, Double Tree Hotel, 2050 Gateway Place,
San Jose, CA 95110.
Website: http://www.dvcon.com
DVCon 2005, which spans a three-day period from February 14-16,
will include a variety of tutorials, panels, sessions and events.
Beginning on Monday, February 14, Mentor Graphics is sponsoring a
tutorial on "Transitioning to SystemVerilog for Verification." The
material in this tutorial will be general to using SystemVerilog for
verification and will benefit anyone seeking guidance on creating a
SystemVerilog-based verification methodology. To round off the day,
Mentor and Synopsys will be co-sponsoring a "We LOVE SystemVerilog"
cocktail reception at 5:00 p.m. to celebrate the possibilities that
SystemVerilog offers, as well as to answer questions.
On Tuesday, February 15, Robert Hum, the company's vice president
and general manager of the Design & Verification Test Division, will
participate in a panel discussion moderated by John Cooley of ESNUG
and DeepChip. The focus of the panel discussion will be on today's
controversial EDA topics.
Finally, on the last day of the conference, Mentor will be
sponsoring a panel discussion entitled, "What's Next for Design and
Verification Methodology," moderated by Stephen Bailey, product
marketing manager, also of the Design & Verification Test Division.
Panelists will have an opportunity to provide insights into their
organization's initiatives to improve productivity in design and
verification, and share plans to adapt existing or adopting new
methodology and process flows. For more information on this, and other
events, times and locations, please visit DVCon 2005's website at:
http://www.dvcon.com.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of over
$700 million and employs approximately 3,850 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: http://www.mentor.com/.
Mentor Graphics is a registered trademark of Mentor Graphics
Corporation. All other company or product names are the registered
trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics
Suzanne Graham, 503-685-7789
suzanne_graham@mentor.com
or
Barbara Rizzatti, 503-685-0443
barbara_rizzatti@mentor.com
